1. Field of the Invention
The present invention generally relates to a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2010-093558, filed Apr. 14, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
To reduce power consumption of semiconductor devices, power saving has been performed by setting unused circuits to a standby state and making the sections to stop operation.
Since standby current flows through transistors even in this standby state, the current value of the standby current is substantial and not ignorable as semiconductor devices are large-scale.
Japanese Unexamined Patent Application Publication No. 11-31385 mentions that in order to reduce this standby current, there is used the following configuration. A sub-threshold current reduction circuit (SCRC) is provided with a plurality of switch circuits between a main power voltage supply line MVCY that transfers power voltage VCC and a sub-power voltage supply line SVCY that selectively transfers the power voltage VCC or a first voltage smaller by a predetermined value than the power voltage VCC.
The first voltage is selectively transferred by performing on/off control of the switch circuit in response to each of the states of the drive state and the standby state. Japanese Unexamined Patent Application Publication No. 11-31385 discloses a DRAM (Random Access Memory), in which this switch circuit is dispersed and arranged in the surface of the chip of the semiconductor device that halts the supply of the first voltage to a circuit set to the standby state.
Japanese Unexamined Patent Application Publication No. 2007-288004 discloses that in order to reduce the standby current, a driver circuit of a P-channel type MOS (Metal Oxide Semiconductor) transistor (hereinafter, referred to as the P-type transistor) is provided, as a switch. The P-channel type MOS transistor generates sub-power supply potential VCT on the basis of the power supply potential VCC. The P-channel type MOS transistor is disposed between an interconnection of the power supply potential VCC and the P-type transistor of an inverter I2.
A driver circuit of an N-channel type MOS transistor (hereinafter, referred to as the N-type transistor) is provided, as a switch. The N-channel type MOS transistor generates sub-ground potential VST on the basis of ground potential VSS. The N-channel type MOS transistor is disposed between an interconnection of the ground potential VSS and the N-type transistor of the inverter I2.